Eliminating voltage emergencies via software-guided code transformations

Transactions on Architecture and Code Optimization

Volumn 7, Issue 2, 2010, Pages

  Reddi, Vijay Janapa ^a   Campanoni, Simone ^a   Gupta, Meeta S ^a   Smith, Michael D ^a   Wei, Gu Yeon ^a   Brooks, David ^a   Hazelwood, Kim ^b  

^a HARVARD UNIVERSITY   (United States)

^b UNIVERSITY OF VIRGINIA   (United States)

Author keywords

DI dt; Inductive noise; Voltage emergencies; Voltage noise

Indexed keywords

CIRCUIT RELIABILITY; CODE TRANSFORMATION; COLLABORATIVE APPROACH; DI/DT; FUTURE TECHNOLOGIES; HIGH PERFORMANCE PROCESSORS; INDUCTIVE NOISE; INSTRUCTION STREAMS; INTELLIGENT ALGORITHMS; NATURAL VARIATION; PERFORMANCE EFFICIENCY; RECOVERY MECHANISMS; RELIABILITY PROBLEMS; RUN-TIME SOFTWARE; RUNTIME PERFORMANCE; RUNTIMES; SHRINKING FEATURE SIZES; SUPPLY VOLTAGES; SUPPLY-VOLTAGE FLUCTUATION; VOLTAGE EMERGENCIES; VOLTAGE FLUCTUATIONS; VOLTAGE FLUX; VOLTAGE NOISE;

COSINE TRANSFORMS; INTELLIGENT BUILDINGS; METAL RECOVERY; OPTIMIZATION;

MICROPROCESSOR CHIPS;

EID: 77958068228     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1839667.1839674     Document Type: Article

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