DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 381-392

  Gupta, Meeta S ^a   Rangan, Krishna K ^a   Smith, Michael D ^a   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; ERROR CORRECTION; METAL RECOVERY; MICROPROCESSOR CHIPS; SENSORS; TIME MEASUREMENT; VOLTAGE CONTROL;

APPLICATIONS.; ARCHITECTURAL SOLUTIONS; CONVENTIONAL DESIGNS; FEEDBACK LOOPS; INDUCTIVE NOISES; MICROPROCESSOR DESIGNS; MODERN PROCESSORS; OPERATING VOLTAGES; PACKAGE MODELS; PACKAGING TECHNOLOGIES; PEAK CURRENTS; PERFORMANCE PENALTIES; RECOVERY SCHEMES; REORDER BUFFERS; SENSOR CHARACTERISTICS; SOFT ERRORS; STRONG CORRELATIONS; TIMING MARGINS; TIMING VIOLATIONS; VOLTAGE EMERGENCIES; VOLTAGE FLUCTUATIONS; VOLTAGE SENSORS;

COMPUTER ARCHITECTURE;

EID: 57749207483     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658654     Document Type: Conference Paper

References (31)

1. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In MICRO 36: 36th annual IEEE/ACM International Symposium on Microarchitecture, 2003.
2. H. Ando and et al. A 1.3GHz Fifth Generation SPARC64 Microprocessor. IEEE Journal of Solid-State Circuits, 38(11), Nov. 2003.
3. M. Annawaram, E. Grochowski, and P. Reed. Implications of Device Timing Varaiblity on Full Chip Timing. In HPCA '07: High-Performance Computer Architecture, 2007.
4. T. M. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In MICRO 32: 32nd annual ACM/IEEE International Symposium on Microarchitecture, 1999.
5. K. Aygun, M. J. Hill, K. Eilert, R. Radhakrishnan, and A. Levin. Power Delivery for High-Performance Microprocessors. Intel Technology Journal, 9(4), Nov. 2005.
6. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a Framework for Architectural-level Power Analysis and Optimizations. In ISCA, 2000.
7. S. Chatterjee, C. Weaver, and T. Austin. Efficient Checker Processor Design. In MICRO 33: 33rd annual ACM/IEEE international symposium on Microarchitecture, 2000.
8. W. El-Essawy and D. Albonesi. Mitigating Inductive Noise in SMT Processors. In ISLPED, 2004.
9. D. Ernst, N. Kim, S. Das, S. Pant, R. Rao, T. Pham, K. F. C. Ziesler D. Blaauw, T. Austin, and T. Mudge. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. In MICRO'03, 2003.
10. S. M. et al. 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS. IEEE JSSC'95, 30(8), 1995.
11. E. Grochowski, D. Ayers, and V. Tiwari. Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. In HPCA'02, 2002.
12. K. Hazelwood and D. Brooks. Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization. In ISLPED, 2004.
13. D. Herell and B. Becker. Modelling of Power Distribution Systems for High-Performance Microprocessors. In IEEE Transactions on Advanced Packaging, volume 22, October 1999.
14. N. James and et al. Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor. In ISSCC 2007, Feb 2007.
15. R. Joseph, D. Brooks, and M. Martonosi. Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. In Int'l Symposium on High-Performance Computer Architecture, 2003.
16. N. Kirman, M. Kirman, M. Chaudhuri, and J. Martinez. Checkpointed Early Load Retirement. In HPCA '05: 11th International Symposium on High-Performance Computer Architecture, 2005.
17. J. F. Martínez, J. Renau, M. C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors. In MICRO, 2002.
18. S. S. Mukherjee, C. T. Weaver, J. Emer, S. K. Reinhardt, and T. Austin. Measuring Architectural Vulnerability Factors. IEEE MICRO'03, 23(6), November 2003.
19. S. Narayanasamy, G. Pokam, and B. Calder. BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. In ISCA '05, 2005.
20. M. Powell and T. N. Vijaykumar. Exploiting Resonant Behavior to Reduce Inductive Noise. In Int'l Symp. on Computer Architecture, Jun 2004.
21. M. D. Powell and T. N. Vijaykumar. Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. In Int'l Symposium on Low Power Electronics and Design, 2003.
22. E. Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. In FTCS '99: Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, 1999.
23. S. Rusu and et al. A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. IEEE Journal of Solid-State Circuits, 42(1), 2006.
24. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2005.
25. S. Shyam, K. Constantinides, S. Phadke, V. Bertacco, and T. Austin. Ultra Low-Cost Defect Protection for Microprocessor Pipelines. ASPLOS-XII, 2006.
26. L. Smith, R. E. Anderson, and T. Roy. Chip-package Resonance in core Power Supply Structures for a High Power Microprocessor. In Pacific Rim/ASME International Electronic Packaging Technical Conference and Exibition, July 2001.
27. D. J. Sorin, M. M. K. Martin, M. D. Hill, and D. A. Wood. Fast Checkpoint/Recovery to Support Kilo-instruction Speculation and Hardware Fault Tolerance. Computing Science Technical Report CS-TR-2000-1420, University of Wisconsin-Madison, october 2000.
28. L. Spainhower and T. Gregg. G4: A fault-tolerant CMOS mainframe. In FTCS '98: Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, 1998.
29. N. J. Wang and S. J. Patel. ReStore: Symptom-Based Soft Error Detection in Microprocessors. IEEE Trans. Dependable Secur. Comput., 3(3), 2006.
30. C. Weaver and T. M. Austin. A Fault Tolerant Approach to Microprocessor Design. In DSN '01: 2001 International Conference on Dependable Systems and Networks (formerly: FTCS), 2001.
31. S. Wijeratne and et al. A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core. In ISSCC'2006, Feb 2006.