Flip-flop energy/performance versus clock slope and impact on the clock network design

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 6, 2010, Pages 1273-1286

  Alioto, Massimo ^a   Consoli, Elio ^b   Palumbo, Gaetano ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

Clock domain; Clock slope; Clocking; Energy consumption; Flip flops; High speed; Low power; Skew; VLSI

Indexed keywords

CLOCK DOMAIN; CLOCK DOMAINS; ENERGY CONSUMPTION; HIGH-SPEED; LOW POWER;

CMOS INTEGRATED CIRCUITS; ENERGY CONSERVATION; ENERGY DISSIPATION; FLIP FLOP CIRCUITS; JITTER; OPTIMIZATION; SPEED;

CLOCKS;

EID: 77953480241     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2030113     Document Type: Article

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