Statistical clock skew modeling with data delay variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 888-898

  Harris, David ^a   Naffziger, Sam ^b  

^a HARVEY MUDD COLLEGE   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

Clock skew; Clocks; Jitter; Noise; Process variation; Variability

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; JITTER; MONTE CARLO METHODS; PHASE LOCKED LOOPS; RESOURCE ALLOCATION; SPURIOUS SIGNAL NOISE;

CLOCK SKEW MODELING;

MICROPROCESSOR CHIPS;

EID: 0035707479     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974902     Document Type: Article

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