Clock Distribution Methodology for PowerPC™ Microprocessors

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 181-189

  Ganguly, Shantanu ^a,b,c,d,e   Lehther, Daksh ^a,f,g   Pullela, Satyamurthy ^a,h,i  

^a MOTOROLA INC   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c SYRACUSE UNIVERSITY   (United States)

^d Sector CAD Organization   (United States)

^e PowerPC CAD Organization   (United States)

^f ANNA UNIVERSITY   (India)

^g IOWA STATE UNIVERSITY   (United States)

^h INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

ⁱ UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; TIMING CIRCUITS;

CLOCK DISTRIBUTION METHODOLOGY;

MICROPROCESSOR CHIPS;

EID: 0031170554     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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