Clustering and load balancing for buffered clock tree synthesis

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 217-223

  Mehta, Ashish D ^a   Chen, Yao Ping ^a   Menezes, Noel ^a   Wong, D F ^a   Pileggi, Lawrence T ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS;

CLOCK TREE SYNTHESIS; ELMORE DELAY;

TIMING CIRCUITS;

EID: 0031353135     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)