Clock distribution using multiple voltages

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 145-150

  Pangjun, Jatuchai ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; ENERGY CONSERVATION; ENERGY DISSIPATION;

REDUCED SWING BUFFERS;

TIMING CIRCUITS;

EID: 0033362386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313902     Document Type: Article

References (18)