Jitter characteristic in charge recovery resonant clock distribution

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 7, 2007, Pages 1618-1625

  Mesgarzadeh, Behzad ^a,b   Hansson, Martin ^a,b   Alvandpour, Atila ^a,b  

^a IEEE   (Sweden)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Charge recovery resonant clocking; Clock distribution network; Jitter peaking; Jitter suppression; Low power

Indexed keywords

CHARGE RECOVERY; CLOCK DISTRIBUTION NETWORK; JITTER SUPPRESSION TECHNIQUE; RESONANT CLOCK DISTRIBUTION;

CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; ELECTRIC NETWORK ANALYSIS; PIPELINE PROCESSING SYSTEMS; RESONANT CIRCUITS;

TIMING JITTER;

EID: 34347212431     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.896691     Document Type: Conference Paper

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