Individual flip-Flops with gated clocks for low power datapaths

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 6, 1997, Pages 507-516

  Lang, Tomas ^a   Musoll, Enric ^b,c   Cortadella, Jordi ^b  

^a University of California at Irvine   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Flip flop energy model; Gated clocks; Low power datapaths

Indexed keywords

ENERGY DISSIPATION; FLIP FLOP CIRCUITS; MOBILE RADIO SYSTEMS;

FLIP FLOP ENERGY MODELS; LOW POWER DATAPATHS;

DIGITAL CIRCUITS;

EID: 0031162009     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.592586     Document Type: Article

References (14)

1. M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-based sequential logic optimization for low power," IEEE Trans. VLSI Syst.. vol. 2, pp. 42636, Dec. 1994.
2. R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, "A symbolic method to reduce power consumption of circuits containing false paths," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1994, pp. 368-371.
3. L. Benin! and G. De Micheli, "Transformation and synthesis of FSM's for low-power gated-clock implementation," in Int. Symp. Low Power Design, Apr. 1995, pp. 21-26.
4. A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Boston, MA: Kluwer Academic, 1995.
5. M. D. Ercegovac and T. Lang, "Low-power accumulator (correlator), in Proc. Int. Symp. Low Power Electron., Oct. 1995, pp. 30-31.
6. S. Gary, P. Ippolito, G. Gerosa, C. Dietz, J. Eno, and H. Sânchez, "PowerPC 603, a microprocessor for portable computers," IEEE Design Test of Comput., pp. 14-23, Winter 1994.
7. P. Groeneveld and P. Stravens, "Ocean: The Sea-of-Gates design system," Tech. Rep., Delft Univ. Tech., 1993.
8. R. Hossain, L. D. Wronski, and A. Albicki, "Low power design using double edge triggered flip-flops," IEEE Trans. VLSI Syst., vol. 2, pp. 261-265, June 1994.
9. U. Ko, P. T. Balsara, and W. Lee, "A self-timed method to minimize spurious transitions in low power CMOS circuits," in Proc. Int. Symp. Low Power Electron., Oct. 1994, pp. 62-63.
10. T. Lang, E. Musoll, and J. Cortadella, "Individual flip-flops with gated clocks for low-power datapaths," Tech. Rep., UPC-DAC- 1996-26, Dept. Comput. Architect., Polytech. Univ. Catalonia, 1996, ftp://ftp.ac.upc.eS/pub/reports/DAC/1996/UPC-DAC-1996-26.ps.
11. LSI LOGIC. LCA500K Preliminary Design Manual, Nov. 1994.
12. T. H. Meng, B. M. Gordon, E. K. Tsern, and A. C. Hung, "Portable video-on-demand in wireless communication," Proc. IEEE, vol. 83, pp. 659-680, Apr. 1995.
13. S. Sheng, A. P. Chandrakasan, and R. W. Brodersen, "A portable multimedia terminal," IEEE Commun. Mag., pp. 64-75, Dec. 1992.
14. A. J. van Gerenden, "SLS: An efficient switch-level timing simulator using min-max voltage waveforms," in Proc. VLSI 89 Conf., Aug. 1989, pp. 79-88.