High-performance microprocessor design

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 5, 1998, Pages 676-685

  Gronowski, Paul E ^a,b   Bowhill, William J ^a,b   Preston, Ronald P ^a,b   Gowan, Michael K ^b   Allmon, Randy L ^a,b  

^a IEEE   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

Alpha; CMOS digital integrated circuits; Computer architecture; Flip flops; Integrated circuit design; Logic design; Microprocessors

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; PERFORMANCE;

ALPHA MICROPROCESSOR;

DIGITAL INTEGRATED CIRCUITS;

EID: 0032071753     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.668981     Document Type: Article

References (14)

1. D. Dobberpuhl et al., "A 200 MHz 64 b dual-issue CMOS microprocessor," IEEE J. Solid-State Circuits, vol. 27, pp. 106-107, Nov. 1992.
2. W. Bowhill et al., "A 300 MHz 64 b quad-issue CMOS microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 182-183.
3. B. Gieseke et al., "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 176-177.
4. R. Sites and R. Witek, Alpha AXP Architecture Reference Manual, 2nd ed. Boston, MA: Digital, 1995.
5. J. Edmondson et al., "Superscalar instruction execution in the 21164 Alpha microprocessor," IEEE Micro, vol. 15, pp. 33-43, Apr. 1995.
6. J. Kowaleski et al., "A dual-execution pipelined floating-point CMOS processor," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 358-359.
7. B. Benschneider et al., "A 300-MHz 64-b quad-issue CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 30, pp. 1203-1214, Nov. 1995.
8. L. Heller and W. Griffin, "Cascode voltage switch logic: A differential CMOS logic family," in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 16-17.
9. D. Priore, "Inductance on silicon for sub-micron CMOS VLSI," in 1993 Symp. VLSI Circuits, Dig. Tech. Papers, May 1993, pp. 17-18.
10. P. Gronowski and W. Bowhill, "Dynamic logic and latches: Practical implementation methods and circuit examples used on the ALPHA 21164," in 1996 Symp. VLSI Circuits - Proc. VLSI Circuits Workshop.
11. D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor," Digital Tech. J., vol. 4, no. 4, pp. 35-50, 1992.
12. P. Larsson and C. Svensson, "Impact of clock slope on true single phase clocked (TSPC) CMOS circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 723-726, June 1994.
13. W. Bowhill et al., "Circuit implementation of a 300-MHz 64-bit second-generation CMOS alpha CPU," Digital Tech. J., vol. 7, no. 1, pp. 100-118, 1995.
14. P. Gronowski et al., "A 433 MHz 64 b quad-issue CMOS RISC microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 222-223.