Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 262-273

  Madan, Niti ^a   Zhao, Li ^b   Muralimanohar, Naveen ^a   Udipi, Aniruddha ^a   Balasubramonian, Rajeev ^a   Iyer, Ravishankar ^b   Makineni, Srihari ^b   Newell, Donald ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache and memory hierarchy; Multi core processors; Non uniform cache architecture (NUCA); On chip networks; Page coloring; SRAM DRAM cache reconfiguration

Indexed keywords

BUFFER STORAGE; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL INTEGRATED CIRCUITS;

CACHE RECONFIGURATIONS; MEMORY HIERARCHY; MULTI-CORE PROCESSOR; NON-UNIFORM CACHE ARCHITECTURES; ON-CHIP NETWORKS; PAGE COLORINGS;

INTEGRATED CIRCUIT DESIGN;

EID: 64949203821     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798261     Document Type: Conference Paper

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