Nahalal: Cache organization for Chip Multiprocessors

IEEE Computer Architecture Letters

Volumn 6, Issue 1, 2007, Pages 21-24

  Guz, Zvika ^a   Keidar, Idit ^a   Kolodny, Avinoam ^a   Weiser, Uri C ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; DATA REDUCTION;

CACHE ACCESS LATENCY; CHIP MULTIPROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 34547644997     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2007.6     Document Type: Article

References (12)

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