Dynamically managing the communication-parallelism trade-off in future clustered processors

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2003, Pages 275-286

  Balasubramonian, Rajeev ^a   Dwarkadas, Sandhya ^a   Albonesi, David H ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MICROPROGRAMMING; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

CLUSTERED MICROARCHITECTURE; INSTRUCTION LEVEL PARALLELISM;

MICROPROCESSOR CHIPS;

EID: 0038346226     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/859618.859650     Document Type: Conference Paper

References (40)

1. V. Agarwal, M. Hrishikesh, S. Keckler, and D. Burger. Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures. In Proceedings of the ISCA-27, pages 248-259, 2000.
2. A. Aggarwal and M. Franklin. An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. In Proceedings of ISPASS, 2001.
3. H. Akkary and M. Driscoll. A Dynamic Multithreading Processor. In Proceedings of MICRO-31, 1998.
4. D. Albonesi. Dynamic IPC/clock rate optimization. Proceedings of the 25th International Symposium on Computer Architecture, pages 282-292, June 1998.
5. S. I. Association. The National Technology Roadmap for Engineers. Technical report, 1999.
6. R. I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In Proceedings of ISCA-28, July 2001.
7. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In Proceedings of MICRO-33, pages 245-257, Dec 2000.
8. A. Baniasadi and A. Moshovos. Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors. In Proceedings of MICRO-33, pages 337-347, Dec 2000.
9. D. Burger and T. Austin. The Simplescalar Toolset, Version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, June 1997.
10. A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D. Albonesi. An Adaptive Issue Queue for Reduced Power at High Performance. In Workshop on Power-Aware Computer Systems (PACS2000, held in conjunction with ASPLOS-IX), Nov 2000.
11. R. Canal, J. M. Parcerisa, and A. Gonzalez. Dynamic Cluster Assignment Mechanisms. In Proceedings of HPCA-6, 2000.
12. R. Canal, J. M. Parcerisa, and A. Gonzalez. Dynamic Code Partitioning for Clustered Architectures. International Journal of Parallel Programming, 29(1):59-79, 2001.
13. A. Capitanio, N. Dutt, and A. Nicolau. Partitioned Register Files for VLIWs: A Preliminary Analysis of Trade-offs. In Proceedings of MICRO-25, 1992.
14. S. Cho, P.-C. Yew, and G. Lee. Access Region Locality for High-Bandwidth Processor Memory System Design. In Proceedings of MICRO-32, pages 136-146, 1999.
15. S. Cho, P.-C. Yew, and G. Lee. Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. In Proceedings of ISCA-26, pages 100-110, 1999.
16. A. Dhodapkar and J. E. Smith. Managing Multi-Configurable Hardware via Dynamic Working Set Analysis. In Proceedings of ISCA-29, May 2002.
17. K. Farkas, P. Chow, N. Jouppi, and Z. Vranesic. The Multicluster Architecture: Reducing Cycle Time through Partitioning. In Proceedings of MICRO-30, 1997.
18. B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of ISCA-28, July 2001.
19. D. Folegnani and A. Gonzalez. Reducing Power Consumption of the Issue Logic. In Workshop on Complexity-Effective Design (WCED2000, held in conjunction with ISCA-27), June 2000.
20. S. Ghiasi, J. Casmira, and D. Grunwald. Using IPC Variations in Workloads with Externally Specified Rates to Reduce Power Consumption. In Workshop on Complexity Effective Design (WCED2000, held in conjunction with ISCA-27), June 2000.
21. M. Huang, J. Renau, and J. Torrellas. Positional Adaptation of Processors: Applications to Energy Reduction. In Proceedings of ISCA-30, June 2003.
22. M. Huang, J. Reneau, S. Yoo, and J. Torrellas. A Framework for Dynamic Energy Efficiency and Temperature Management. In Proceedings of MICRO-33, pages 202-213, Dec 2000.
23. S. Keckler and W. Dally. Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. In Proceedings of ISCA-19, May 1992.
24. R. Kessler. The Alpha 21264 Microprocessor. IEEE Micro, 19(2):24-36, March/April 1999.
25. C. Lee, M. Potkonjak, and W. Mangione-Smith. Media-bench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proceedings of MICRO-30, pages 330-335, 1997.
26. P. Lowney, S. Freudenberger, T. Karzes, W. Lichtenstein, R. Nix, J. O'Donnell, and J. Ruttenberg. The Multiflow Trace Scheduling Compiler. Journal of Supercomputing, 7(1-2):51-142, May 1993.
27. D. Matzke. Will Physical Scalability Sabotage Performance Gains? IEEE Computer, 30(9):37-39, Sept 1997.
28. R. Nagarajan, K. Sankaralingam, D. Burger, and S. Keckler. A Design Space Evaluation of Grid Processor Architectures. In Proceedings of MICRO-34, Dec 2001.
29. S. Palacharla, N. Jouppi, and J. Smith. Complexity-Effective Superscalar Processors. In Proceedings of ISCA-24, 1997.
30. J.-M. Parcerisa, J. Sahuquillo, A. Gonzalez, and J. Duato. Efficient Interconnects for Clustered Microarchitectures. In Proceedings of PACT, Sep 2002.
31. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources. In Proceedings of MICRO-34, Dec 2001.
32. N. Ranganathan and M. Franklin. An Empirical Study of Decentralized ILP Execution Models. In Proceedings of ASPLOS-VIII, pages 272-281, 1998.
33. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith. Trace Processors. In Proceedings of MICRO-30, 1997.
34. P. Shivakumar and N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. Technical Report TN-2001/2, Compaq Western Research Laboratory, August 2001.
35. G. Sohi, S. Breach, and T. Vijaykumar. Multiscalar Processors. In Proceedings of ISCA-22, 1995.
36. D. Tullsen, S. Eggers, and H. Levy. Simultaneous Multi-threading: Maximizing On-Chip Parallelism. In Proceedings of ISCA-22, pages 392-403, 1995.
37. E. Tune, D. Liang, D. Tullsen, and B. Calder. Dynamic Prediction of Critical Path Instructions. In Proceedings of HPCA-7, Jan 2001.
38. S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep Submicron High-Performance I-Caches. In Proceedings of HPCA-7, Jan 2001.
39. A. Yoaz, M. Erez, R. Ronen, and S. Jourdan. Speculation Techniques for Improving Load Related Instruction Scheduling. In Proceedings of ISCA-26, pages 42-53, 1999.
40. V. Zyuban and P. Kogge. Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Transactions on Computers, Mar 2001.