Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2005, Pages 346-356

  Speight, Evan ^a   Shafi, Hazim ^a   Zhang, Lixin ^a   Rajamony, Ram ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE TRANSFERS; CACHING; ON-CHIP DIRECTORY; SILICON CHIPS;

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; SILICON;

BUFFER STORAGE;

EID: 27544498313     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2005.8     Document Type: Conference Paper

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