The Alpha 21364 network architecture

IEEE Micro

Volumn 22, Issue 1, 2002, Pages 26-35

  Mukherjee, Shubhendu S ^a,b   Bannon, Peter ^b   Lang, Steven ^b   Spink, Aaron ^b   Webb, David ^b  

^a SHR1 T25 ^*  (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ARCHITECTURE;

BANDWIDTH; BUFFER STORAGE; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; PROGRAM PROCESSORS; ROUTERS; SERVERS;

MICROPROCESSOR CHIPS;

EID: 0036167929     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.988687     Document Type: Article

References (7)

1. Alpha 21364: A scalable single chip SMP
2. A 1.2 GHz alpha microprocessor with 44.8 GB/sec of chip pin bandwidth
3. Spider: A high-speed network interconnect
4. Alpha 21364: A single-chip shared memory multiprocessor
5. Virtual channel flow control
6. A new theory of deadlock-free adaptive routing in wormhole networks
7. Self-tuned congestion control for multiprocessor networks