Interconnect design considerations for large NUCA caches

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 369-380

  Muralimanohar, Naveen ^a   Balasubramonian, Rajeev ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

Cache models; Interconnect; Memory hierarchies; Network on chip; Non uniform cache architecture

Indexed keywords

CACHE BLOCK PLACEMENT; CACHE MODELS; MEMORY HIERARCHIES; NON UNIFORM CACHE ARCHITECTURES (NUCA);

ELECTRIC POWER UTILIZATION; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM PROCESSORS;

CACHE MEMORY;

EID: 35348847741     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250708     Document Type: Conference Paper

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