Montecito: A dual-core, dual-thread itanium processor

IEEE Micro

Volumn 25, Issue 2, 2005, Pages 10-20

  McNairy, Cameron ^a   Bhatia, Rohit ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; SERVERS; TRANSISTORS;

DEMAND BASE SWITCHING; ITANIUM PROCESSOR; MULTITHREADING;

MICROPROCESSOR CHIPS;

EID: 20344403770     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.34     Document Type: Article

References (11)

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3. C. McNairy and D. Soltis, "Itanium 2 Processor Microarchitecture," IEEE Micro, vol. 23, no. 2, Mar.-Apr. 2003, pp. 44-55.
4. M. Mock et al., "An Empirical Study of Data Speculation Use on the Intel Itanium 2 Processor," to be published in Proc. Workshop Interaction Between Compilers and Computer Architecture, IEEE CS Press, 2005.
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7. E. Fetzer et al., "The Multi-threaded, Parity Protected, 128 Word Register Files on a Dualcore Itanium Architecture Processor," Int'l Solid State Circuits Conf. Digest of Technical Papers, IEEE Press, 2005, pp. 382-383.
8. C. Poirier et al., "Power and Temperature Control on a 90 nm Itanium Architecture Processor," Int'l Solid State Circuits Conf. 2005 Digest of Technical Papers, IEEE Press, 2005, pp. 304-305.
9. E. Fetzer et al., "Clock Distribution on a Dualcore, Multi-threaded Itanium Architecture Processor," Int'l Solid State Circuits Conf. Digest of Technical Papers, IEEE Press, 2005, pp. 292-293.
10. T. Fischer et al., "A 90 nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor," Int'l Solid State Circuits Conf. Digest of Technical Papers, IEEE Press, 2005, pp. 294-295.
11. C. McNairy and J. Mayfield, "Montecito Error Protection and Mitigation," to be published in Proc. Workshop High-Performance Computing Reliability Issues, IEEE CS Press, 2005.