Distance associativity for high-performance energy-efficient non-uniform cache architectures

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 55-66

  Chishti, Z ^a   Powell, M D ^a   Vijaykumar, T N ^a  

^a Purdue University   (United States)

Author keywords

Computer architecture; Delay; Energy efficiency; Power engineering and energy; Probes; Random access memory; Wire

Indexed keywords

BANDWIDTH; BUFFER STORAGE; COMPUTER ARCHITECTURE; ECONOMIC AND SOCIAL EFFECTS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROBES; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; WIRE;

DELAY; ENERGY EFFICIENT; HIGH BANDWIDTH; NON-UNIFORM ACCESS; NON-UNIFORM CACHE ARCHITECTURE; NON-UNIFORM CACHE ARCHITECTURES; POWER ENGINEERING AND ENERGIES; RANDOM ACCESS MEMORY;

ENERGY EFFICIENCY;

EID: 84944411840     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253183     Document Type: Conference Paper

References (14)

1. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
2. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
3. J. H. Edmondson et al. Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor. Digital Technical Journal, 7(1), 1995.
4. A. Gonzalez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proceedings of the 1995 International Conference on Supercomputing, pages 338-347, July 1995.
5. E. G. Hallnor and S. K. Reinhardt. A fully-associative software-managed cache design. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 107-116, June 2000.
6. T. L. Johnson and W. W. Hwu. Run-time adaptive cache hierarchy management via reference analysis. In 24th International Symposium on Computer Architecture, pages 315-326, July 1997.
7. C. Kim, D. Burger, and S. W. Keckler. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS X), pages 211-222, Oct. 2002.
8. S. D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. Sullivan, and T. Grutkowski. The implementation of the Itanium 2 microprocessor. IEEE Journal of Solid-State Circuits, 37(11):1448-1460, Nov. 2002.
9. M. D. Powell, A. Agarwal, T. N. Vijaykumar, and B. Falsafi. Reducing set-associative cache energy via way-prediction and selective directmapping. In Proceedings of the 34th International Symposium on Microarchitecture (MICRO 34), pages 54-65, Dec. 2001.
10. S. A. Przybylski. Performance-directed memory hierarchy design. Technical Report 366, Stanford University, Sept. 1988.
11. P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power and area model. Technical report, Compaq Computer Corporation, Aug. 2001.
12. A. J. Smith. Cache memories. ACM Computing Surveys (CSUR), 14(3):473-530, 1982.
13. G. Tyson, M. Farrens, J. Matthews, and A. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th International Symposium on Microarchitecture, pages 93-103, Dec. 1995.
14. D. Weiss, J. J. Wuu, and V. Chin. The on-chip 3-mb subarray-based third-level cache on an Itanium microprocessor. IEEE Journal of Solid-State Circuits, 37(11):1523-1529, Nov. 2002.