A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 51-62

  Thoziyoor, Shyamkumar ^a   Ahn, Jung Ho ^b   Monchiero, Matteo ^b   Brockman, Jay B ^a   Jouppi, Norman P ^b  

^a UNIVERSITY OF NOTRE DAME   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; INTEGRATED CIRCUIT DESIGN; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE;

DESIGN AND ANALYSIS; DRAM CHIPS; DRAM TECHNOLOGY; ENERGY DELAY PRODUCT; FUTURE MEMORY; LAST-LEVEL CACHES; MAIN-MEMORY; MEMORY HIERARCHY; MEMORY MODELING; MODELLING TOOLS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 52649139073     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1394608.1382127     Document Type: Conference Paper

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