-
2
-
-
22944440036
-
High Performance Throughput Computing
-
May-June
-
S. Chauchry et al., "High Performance Throughput Computing," IEEE Micro, vol. 25, no. 3, May-June 2005, pp. 32-45.
-
(2005)
IEEE Micro
, vol.25
, Issue.3
, pp. 32-45
-
-
Chauchry, S.1
-
3
-
-
20344374162
-
Niagara: A 32-Way Multithreaded Sparc Processor
-
Mar.-Apr
-
P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, Mar.-Apr. 2005, pp. 21-29.
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 21-29
-
-
Kongetira, P.1
Aingaran, K.2
Olukotun, K.3
-
4
-
-
35349021527
-
-
J. Laudon, Performance/Watt: The New Server Focus, ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), 33, no. 4, Nov. 2005, pp. 5-13, http://www.cse.ucsd.edu/~rakumar/dasCMP05/paper01.pdf.
-
J. Laudon, "Performance/Watt: The New Server Focus," ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), vol. 33, no. 4, Nov. 2005, pp. 5-13, http://www.cse.ucsd.edu/~rakumar/dasCMP05/paper01.pdf.
-
-
-
-
5
-
-
0041527795
-
Intel's90 nm Technology: Moore's Law and More
-
Intel;
-
M. Bohr, "Intel's90 nm Technology: Moore's Law and More," Intel Developer Forum, Intel; ftp://download.intel.com/technology/silicon/ Bohr_IDF_0902.pdf.
-
Intel Developer Forum
-
-
Bohr, M.1
-
6
-
-
20344391930
-
Intel Virtualization Technology
-
May
-
R. Uhlig et al., "Intel Virtualization Technology," Computer, vol. 38, no. 5, May 2005, pp. 48-56.
-
(2005)
Computer
, vol.38
, Issue.5
, pp. 48-56
-
-
Uhlig, R.1
-
8
-
-
0036470119
-
Asim: A Performance Model Framework
-
Feb
-
J. Emer et al., "Asim: A Performance Model Framework," Computer, vol. 35, no. 2, Feb. 2002, pp. 68-76.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 68-76
-
-
Emer, J.1
-
10
-
-
35349014174
-
-
L. Hsu et al., Exploring the Cache Design Space for Large-Scale CMPs, ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), 33, no. 4, Nov. 2005, pp. 24-33, http://www.cse.ucsd.edu/~rakumar/ dasCMP05/paper03.pdf.
-
L. Hsu et al., "Exploring the Cache Design Space for Large-Scale CMPs," ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), vol. 33, no. 4, Nov. 2005, pp. 24-33, http://www.cse.ucsd.edu/~rakumar/ dasCMP05/paper03.pdf.
-
-
-
-
12
-
-
27544456315
-
Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling
-
IEEE CS Press
-
R. Kumar, V. Zyuban, and D.M. Tullsen, "Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 408-419.
-
(2005)
Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05)
, pp. 408-419
-
-
Kumar, R.1
Zyuban, V.2
Tullsen, D.M.3
-
13
-
-
84944411840
-
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
-
IEEE CS Press
-
Z. Chishti, M.D. Powell, and T.N. Vijaykumar, "Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures," Proc. 36th IEEE/ACM Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 55-67.
-
(2003)
Proc. 36th IEEE/ACM Int'l Symp. Microarchitecture (MICRO 03)
, pp. 55-67
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
14
-
-
27544432313
-
Optimizing Replication, Communication, and Capacity Allocation in CMPs
-
IEEE CS Press
-
Z. Chishti, M.D. Powell, and T.N. Vijaykumar, "Optimizing Replication, Communication, and Capacity Allocation in CMPs," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 357-368.
-
(2005)
Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05)
, pp. 357-368
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
15
-
-
8344246922
-
CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms
-
ACM Press
-
R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," Proc. 18th Ann. Int'l Conf. Supercomputing (ICS 04), ACM Press, 2004, pp. 257-266.
-
(2004)
Proc. 18th Ann. Int'l Conf. Supercomputing (ICS 04)
, pp. 257-266
-
-
Iyer, R.1
-
16
-
-
27544498313
-
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
-
IEEE CS Press
-
E. Speight et al., "Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 346-356.
-
(2005)
Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05)
, pp. 346-356
-
-
Speight, E.1
|