TLC: Transmission line caches

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 43-54

  Beckmann, B M ^a   Wood, D A ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Bandwidth; Circuit simulation; Communications technology; Delay; Integrated circuit interconnections; Power transmission lines; System on a chip; Transmission lines; Wires; Wiring

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; CIRCUIT SIMULATION; COMPLEX NETWORKS; COMPUTER ARCHITECTURE; DESIGN; ELECTRIC LINES; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRIC POWER TRANSMISSION; ELECTRIC WIRING; INTEGRATED CIRCUIT DESIGN; PROGRAM PROCESSORS; SYSTEM-ON-CHIP; TRANSMISSION LINE THEORY; WIRE;

COMMUNICATIONS TECHNOLOGY; DELAY; DYNAMIC POWER CONSUMPTION; HIGH PERFORMANCE SYSTEMS; INTEGRATED CIRCUIT INTERCONNECTIONS; MANUFACTURING COMPLEXITY; NON-UNIFORM CACHE ARCHITECTURE; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84944410327     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253182     Document Type: Conference Paper

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