Experimental investigation of the impact of LWR on sub-100-nm device performance

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 1984-1988

  Kim, Hyun Woo ^a   Lee, Ji Young ^a   Shin, Jangho ^a   Woo, Sang Gyun ^a   Cho, Han Ku ^a   Moon, Joo Tae ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Line edge roughness (LER); Line width roughness (LWR); NMOS

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ETCHING; LEAKAGE CURRENTS; LITHOGRAPHY; PHOTORESISTS; SEMICONDUCTOR DEVICE MANUFACTURE; THRESHOLD VOLTAGE;

ETCH RESISTANCE; LINE EDGE ROUGHNESS (LER); LINE WIDTH ROUGHNESS (LWR);

MOSFET DEVICES;

EID: 10644264480     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.839115     Document Type: Article

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