Direct measurement of effects of shallow-trench isolation on carrier profiles in Sub-50 nm N-MOSFETs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 140-141

  Fukutome, H ^a   Momiyama, Y ^a   Tagawa, Y ^a   Kubo, T ^a   Aoyama, T ^a   Arimoto, H ^a   Nara, Y ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; GATES (TRANSISTOR); LEAKAGE CURRENTS; NANOTECHNOLOGY; RANDOM ACCESS STORAGE;

6T-SRAM CELL; CHANNEL CONCENTRATION; SHALLOW-TRENCH ISOLATION (STI); SUB-THRESHOLD LEAKAGE CURRENT;

MOSFET DEVICES;

EID: 33745131794     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469244     Document Type: Conference Paper

References (3)

1. K. Goto, et al., Symp. VLSI Tech., pp. 49 (2003).
2. H. Fukutome, et al., IEDM Tech. Digs., pp. 433 (2004).
3. H. Fukutome, et al., J Vac. Sci. & Technol. B 22, pp. 358 (2004).