An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

IEEE Electron Device Letters

Volumn 22, Issue 6, 2001, Pages 287-289

  Diaz C H ^a   Tao, H J ^a   Ku, Y C ^a   Yen, A ^a   Young, K ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

CMOS gate patterning; Line edge roughness; Lithography

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LITHOGRAPHY; SURFACE ROUGHNESS; THRESHOLD VOLTAGE;

LINE-EDGE ROUGHNESS (LER) EFFECT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035364688     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.924844     Document Type: Article

References (5)

1. Modeling line edge roughness effects in sub 100 nm gate length devices
2. Semiconductor Industry Association
3. Threshold voltage model for deep sub-micrometer MOSFETs
4. A 0.13 μm technology with 193 nm lithography an low-k/Cu interconnect for high performance applications