Atomistic 3D Process/Device Simulation Considering Gate Line-Edge Roughness and Poly-Si Random Crystal Orientation Effects

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 241-244

  Hane, Masami ^a   Ikezawa, Takeo ^a   Ezaki, Tatsuya ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LINE-EDGE ROUGHNESS (LER); SPIKE ANNEALING;

ANNEALING; COMPUTER SIMULATION; CRYSTAL ORIENTATION; DIFFUSION; ELECTROSTATICS; GATES (TRANSISTOR); ION IMPLANTATION; MOLECULAR DYNAMICS; MONTE CARLO METHODS; MOSFET DEVICES; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING; SURFACE ROUGHNESS; THRESHOLD VOLTAGE;

POLYSILICON;

EID: 0842331392     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. P. Oldiges, et al., Proc. SISPAD, p.131 (2000)
2. T. Linton, IEDM Tech. Digs., p.303 (2002)
3. J.A. Croon, et al., IEDM Tech. Digs., p.307 (2002)
4. S. Kaya, et al., Proc. SISPAD, p.78 (2001)
5. T. Ezaki, et al., IEDM Tech. Digs., p.311 (2002)
6. M. Hane, et al., IEDM Tech. Digs., p.843 (2001)
7. M. Hane and T. Ikezawa, Proc. International Workshop on Junction Technology, p.75 (2002)