A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 84-85

  Yasutake, N ^a   Ohuchi, K ^a   Fujiwara, M ^a   Adachi, K ^a   Hokazono, A ^a   Kojima, K ^a   Aoki, N ^a   Suto, H ^a   Watanabe, T ^a   Morooka, T ^a   Mizuno, H ^b   Magoshi, S ^b   Shimizu, T ^b   Mori, S ^b   Oguma, H ^b   Sasaki, T ^b   Ohmura, M ^b   Miyano, K ^b   Yamada, H ^b   Tomita, H ^b   Matsushita, D ^b   Muraoka, K ^b   Inaba, S ^a   Takayanagi, M ^a   Ishimaru, K ^a   Ishiuchi, H ^a   more..

^a SoC Research and Development Center   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

CMOS; Elevated source drain extension; FLA; Metal gate; SiON

Indexed keywords

ANNEALING; ELECTRIC CURRENTS; ELECTRODES; GATES (TRANSISTOR); LEAKAGE CURRENTS; LITHOGRAPHY; MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTING SILICON COMPOUNDS;

CMOSFET DEVICES; GATE DIELECTRICS; LOW OPERATING POWER (LOP); PLASMA NITRIDATION;

CMOS INTEGRATED CIRCUITS;

EID: 4544276950     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345407     Document Type: Conference Paper

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