Interconnect IP node for future system-on-chip designs

Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002

Volumn , Issue , 2002, Pages 116-120

  Saastamoinen, Ilkka ^a   Sigüenza Tortosa, David ^a   Nurmi, Jari ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

INTERNAL ARCHITECTURE; ON CHIP COMMUNICATION; PACKET-BASED COMMUNICATION; REUSABLE COMPONENTS; ROUTING CONTROLLERS; SOC (SYSTEM ON CHIP); STANDARDIZED INTERFACES; SYSTEM ON CHIP DESIGN;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84931029907     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994599     Document Type: Conference Paper

References (9)

1. M. Sgroi et al., "Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design," 38th Design Automation Conference, Las Vegas, USA, Jun. 2001, 6 pages.
2. P. Guerrier and A. Greiner, "A Generic Architecture for On- Chip Packet-Switched Interconnections," Proc. DATE 2000, Paris, France, March 2000, pp. 250-256.
3. A. Hemani et al., "Network on a Chip: An Architecture for Billion Transistor Era," Proc. NORCHIP 2000, Turku, Finland, November 2000, pp. 294-301.
4. J. A. J. Leiten et al., "Stream Communication between Real- Time Tasks in a High-Performance Multiprocessor," Proc. DATE 1998, Paris, France, February 1998, pp. 125-131.
5. I. Saastamoinen et al., "Interconnect IP for Gigascale Systemon- Chip", 15th European Conference on Circuit Theory and Design, Espoo, Finland, August 2001, pp. 281-284.
6. VSI Alliance, "On-Chip Bus Development Working Group Virtual Component Interface Standard Version 2 (OCB 2 2.0)," April 2001, 132 pages.
7. J. Muttersbach et al., "Globally-asynchronous locallysynchronous architectures to simplify the design of on-chip systems," Proc. 12th Annual IEEE International ASIC/SOC Conference, Washington, USA, Sept. 1999, pp. 317 - 321.
8. IEEE Standard for Scalable Coherent Interface (SCI), IEEE Std 1569-1992, 1993, 270 pages.
9. J. Lähteenmäki et al., "General Bus Interface for IP Designs," Proc. International Workshop on IP Based Synthesis and System Design, Grenoble, France, Dec. 1999, 4 pages.