High performance sub-40nm CMOS devices on SOI for the 70nm technology node

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 625-628

  Narasimha, S ^a   Ajmera, A ^a   Park, H ^a   Schepis, D ^a   Zamdmer, N ^a   Jenkins, K A ^a   Plouchart, J O ^a   Lee, W H ^a   Mezzapelle, J ^a   Bruley, J ^a   Doris, B ^a   Sleight, J W ^a   Fung, S K ^a   Ku, S H ^a   Mocuta, A C ^a   Yang, I ^a   Gilbert, P V ^a   Muller, K P ^a   Agnello, P ^a   Welser, J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; FIELD EFFECT TRANSISTORS; FREQUENCY RESPONSE; INTEGRATED CIRCUIT MANUFACTURE; OXIDATION; POLYSILICON; SEMICONDUCTOR DOPING; SIGNAL PROCESSING;

GATE DELAY; PHYSICAL GATE LENGTH; SATURATION CURRENT;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0035714396     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)