A fully planalized 8m bit ferroelectric RAM with 'chain' cell structure

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 113-114

  Ozaki, T ^a   Iba, J ^a   Yamada, Y ^a   Kanaya, H ^a   Morimoto, T ^a   Hidaka, O ^a   Taniguchi, A ^a   Kumura, Y ^a   Yamakawa, K ^a   Oowaki, Y ^a   Kunishima, I ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; FERROELECTRIC DEVICES; METALLIZING; TRANSISTORS;

FERROELECTRIC RANDOM ACCESS MEMORY (FERAM);

RANDOM ACCESS STORAGE;

EID: 0034796394     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)