Sub-60 nm physical gate length SOI CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 431-434

  Yang, I Y ^a   Chen, K ^a   Smeys, P ^a   Sleight, J ^a   Lin, L ^a   Ieong, M ^a   Nowak, E ^a   Fung, S ^a   Maciejewski, E ^a   Varekamp, P ^a   Chu, W ^a   Park, H ^a   Agnello, P ^a   Crowder, S ^a   Assaderaghi, F ^a   et al , ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY;

SHORT CHANNEL EFFECTS; TURN OFF CHARACTERISTICS;

CMOS INTEGRATED CIRCUITS;

EID: 0033339637     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)