45-nm gate length CMOS technology and beyond using steep halo

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 49-51

  Wakabayashi, H ^a   Ueki, M ^b   Narihiro, M ^b   Fukai, T ^b   Ikezawa, N ^b   Matsuda, T ^b   Yoshida, K ^b,c   Takeuchi, K ^b   Ochiai, Y ^b   Mogami, T ^b   Kunio, T ^b  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b NEC CORPORATION   (Japan)

^c NEC Hitachi Memory Incorporated   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; RAPID THERMAL ANNEALING; SEMICONDUCTOR DEVICE MANUFACTURE;

HIGH RAMP RATE SPIKE ANNEALING (HRR-SA);

CMOS INTEGRATED CIRCUITS;

EID: 0034454556     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2000.904256     Document Type: Article

References (8)