Physical design of a fourth-generation POWER GHz microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 451, Issue , 2001, Pages 232-233

  Anderson, Carl J ^a   Petrovick, John ^a   Keaty, John M ^a   Warnock, James ^a   Nussbaum, Gary ^a   Tendler, Joel M ^a   Carter, Criag ^a   Chu, Sam ^a   Clabes, Joachim ^a   DiLullo, Jack ^a   Dudley, Peter ^a   Harvey, Paul ^a   Krauter, Byron ^a   LeBlanc, John ^a   Lu, Pong Fei ^a   McCredie, Bradley ^a   Plum, Gerald ^a   Restle, Phillip J ^a   Runyon, Steve ^a   Scheuermann, Michael ^a   Schmidt, Steve ^a   Wagoner, James ^a   Weiss, Rick ^a   Weitzel, Steve ^a   Zoric, Brian ^a   more..

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MACROS; MULTICHIP MODULES; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

POWER MICROPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0035054909     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISSCC.2001.912617     Document Type: Article

References (1)

1. Power4 focuses on memory bandwidth