70 nm gate length CMOS technology with 1.0 V operation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 14-15

  Ono, A ^a   Fukasaku, K ^a   Matsuda, T ^a   Fukai, T ^a   Ikezawa, N ^a   Imai, K ^a   Horiuchi, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION;

GATE DIELECTRICS; SOURCE/DRAIN EXTENSIONS FORMATIONS;

VLSI CIRCUITS;

EID: 0033712801     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)