An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 257-260

  Thompson, S ^a   Alavi, M ^a   Arghavani, R ^a   Brand, A ^a   Bigwood, R ^a   Brandenburg, J ^a   Crew, B ^a   Dubin, V ^a   Hussein, M ^a   Jacob, P ^a   Kenyon, C ^a   Lee, E ^a   McIntyre, B ^a   Ma, Z ^a   Moon, P ^a   Nguyen, P ^a   Prince, M ^a   Schweinfurth, R ^a   Sivakumar, S ^a   Smith, P ^a   Stettler, M ^a   Tyagi, S ^a   Wei, M ^a   Xu, J ^a   Yang, S ^a   Bohr, M ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LITHOGRAPHY; LOGIC DESIGN; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS; VOLTAGE MEASUREMENT;

ENHANCED GENERATION LOGIC TECHNOLOGY; SATURATION DRIVE CURRENTS;

NANOTECHNOLOGY;

EID: 0035715842     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979479     Document Type: Article

References (3)