A unified approach to reduce SOC test data volume, scan power and testing time

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 3, 2003, Pages 352-362

  Chandra, Anshuman ^a   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

Author keywords

Alternating run length code; Embedded core testing; Scan testing; Switching activity; System on a chip test; Test data compression; Test resource partitioning

Indexed keywords

CODES (SYMBOLS); DATA COMPRESSION; DATA REDUCTION; INTEGRATED CIRCUIT LAYOUT;

EMBEDDED CORE TESTING; SCAN TESTING; SYSTEM ON CHIP; TEST RESOURCE PARTITIONING;

INTEGRATED CIRCUIT TESTING;

EID: 0037345209     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.807895     Document Type: Article

References (38)

1. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," in Proc. VLSI Test Symp., 1993, pp. 4-9.
2. I. Hamzaoglu and J. H. Patel, "Reducing test application time for full scan embedded cores," in Proc. Int. Symp. Fault-Tolerant Comput., 1999, pp. 260-267.
3. F. F. Hsu, K. M. Butler, and J. H. Patel, "A case study on the implementation of Illinois scan architecture," in Proc. Int. Test Conf., 2001, pp. 538-547.
4. A. Chandra and K. Chakrabarty, "Test resource partitioning for SOCs." IEEE Design Test Comput., vol. 18, pp. 80-91, Sept.-Oct. 2001.
5. A. Jas and N. A. Touba, "Test vector decompression via cyclical scan chains and its application to testing core-based design," in Proc. Int. Test Conf., 1998, pp. 458-464.
6. A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes," IEEE Trans. Computer-Aided Design, vol. 20, pp. 355-368, Mar. 2001.
7. P. T. Gonciari, B. Al-Hashimi, and N. Nicolici, "Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression," in Proc. Design, Automation, Test Eur. Conf., 2002, pp. 604-611.
8. S. Kajihara, K. Taniguchi, I. Pomeranz, and S. M. Reddy, "Test data compression using don't-care identification and statistical encoding," in Proc. Int. Workshop Electron. Design, Test, Applicat., 2002, pp. 413-416.
9. R. Dorsch and H.-J. Wunderlich, "Tailoring ATPG for embedded testing," in Proc. Int. Test Conf., 2001, pp. 530-537.
10. A. El-Maleh, S. al Zahir, and E. Khan, "A geometric-primitives-based compression scheme for testing systems-on-chip," in Proc. VLSI Test Symp., 2001, pp. 54-59.
11. I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," in Proc. ACM/IEEE Design Automation Conf., 2001, pp. 151-155.
12. A. Khoche, E. Volkerink, J. Rivoir, and S. Mitra, "Test vector compression using EDA-ATE synergies," in Proc. VLSI Test Symp., 2002, pp. 97-102.
13. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, "OPMISR: the foundation for compressed ATPG vectors," in Proc. Int. Test Conf., 2001, pp. 748-757.
14. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. Comput., vol. 44, pp. 223-233, Feb. 1995.
15. N. Nicolici and B. M. Al-Hashimi, "Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits," in Proc. IEEE/ACM Design, Automation, Test Eur. Conf., Mar. 2000, pp. 715-722.
16. L. Whetsel, "Adapting scan architectures for low power operation," in Proc. Int. Test Conf., 2000, pp. 863-872.
17. J. Saxena, K. Butler, and L. Whetsel, "An analysis of power reduction techniques in scan testing," in Proc. Int. Test Conf., 2001, pp. 670-677.
18. P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H.-J. Wunderlich, "A modified clock scheme for a low power BIST test pattern generator," in Proc. VLSI Test Symp., 2001, pp. 306-311.
19. F. Corno, M. Rebaudengo, and M. S. Reorda, "Low power BIST via nonlinear hybrid cellular automata," in Proc. VLSI Test Symp., 2000, pp. 29-34.
20. S. Gerstendörfer and H.-J. Wunderlich, "Minimized power consumption for scan-based BIST," in Proc. Int. Test Conf., 1999, pp. 77-84.
21. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "A test vector inhibiting technique for low energy BIST design," in Proc. VLSI Test Symp., 1999, pp. 407-412.
22. L. Xu, Y. Sun, and H. Chen, "Scan solution for testing power and testing time," in Proc. Int. Test Conf., 2001, pp. 652-659.
23. S. Wang and S. K. Gupta, "ATPG for heat dissipation minimization during scan testing," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 614-619.
24. V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, "Techniques for minimizing power dissipation in scan and combinational circuits during test application," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1325-1333, Dec. 1998.
25. I. Pomeranz, S. M. Reddy, and R. Guo, "Static Test compaction for synchronous sequential circuits based on vector restoration," IEEE Trans. Computer-Aided Design, pp. 1040-1049, July 1999.
26. R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proc. VLSI Test Symp., 2000, pp. 35-40.
27. V. Iyengar and K. Chakrabarty, "System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints," IEEE Trans. Computer-Aided Design, vol. 21, pp. 1088-1094, Sept. 2002.
28. K. Chakrabarty, "Test scheduling for core-based systems using mixed-integer linear programming," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1163-1174, Oct. 2000.
29. M. Sugihara, H. Date, and H. Yasuura, "A novel test methodology for core-based system LSI's and a testing time minimization problem," in Proc. Int. Test Conf., 1998, pp. 465-472.
30. Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Summan, Y. Zaidan and S. M. Reddy, "Resource allocation and test scheduling for concurrent test of core-based SOC design," in Proc. Asian Test Symp., 2001, pp. 265-270.
31. Y. Huang, S. M. Reddy, W.-T. Cheng, P. Reuter, C.-C. Tsai, N. Mukherjee, O. Summan, and Y. Zaidan, "Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm," in Proc. Eur. Test Workshop Dig. Papers, 2002, pp. 35-41.
32. P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Power profile manipulation: a new approach for reducing test application time under power constraint," IEEE Trans. Computer-Aided Design, vol. 21, pp. 1217-1225, Oct. 2002.
33. A. Chandra and K. Chakrabarty, "Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression," in Proc. VLSI Test Symp., 2001, pp. 42-47.
34. ____, "Low-power scan testing and test data compression for system-on-a-chip," IEEE Trans. Computer-Aided Design, vol. 21, pp. 597-604, May 2002.
35. P. Rosinger, P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, "Simultaneous reduction in volume of test data and power dissipation for system-on-a-chip," Electron. Lett., vol. 37, no. 24, p. 1434-1436, Nov. 2001.
36. I. Hamzaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits," in Proc. Int. Conf. Computer-Aided Design, 1998, pp. 283-289.
37. D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, and K. Stawiasz, "High-speed serializing/de-serializing design-for-test methods for evaluating a 1 GHz microprocessor," in Proc. VLSI Test Symp., 1998, pp. 234-238.
38. M. Berkelaar, (1999) Ipsolve, Vers. 3.0. Eindhoven Univ. of Tech. Eindhoven, The Netherlands, [Online] http://ftp.ics.ele.tue.nl/pub/lp_solve