Reducing test application time for full scan embedded cores

Proceedings - Annual International Conference on Fault-Tolerant Computing

Volumn , Issue , 1999, Pages 260-267

  Hamzaoglu, Ilker ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; FAST FOURIER TRANSFORMS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; SEQUENTIAL CIRCUITS; VECTORS;

FULL SCAN EMBEDDED CORES; MULTIPLE SCAN CHAINS; PARALLEL SERIAL FULL SCAN;

RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0032597651     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (18)