Test data compression using don't-care identification and statistical encoding

Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002

Volumn , Issue , 2002, Pages 413-416

  Kajihara, Seiji ^a,b   Taniguchi, Kenjiro ^a   Pomeranz, Irith ^b   Reddy, Sudhakar M ^c  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b Purdue University   (United States)

^c UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENCODING (SYMBOLS);

BENCHMARK CIRCUIT; DON'T-CARES; FAULT COVERAGES; LOGIC VALUES; TEST DATA COMPRESSION; TEST SETS; TEST VECTORS; TEST-DATA VOLUME;

DATA COMPRESSION;

EID: 0012484170     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994661     Document Type: Conference Paper

References (8)

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2. I. Hamzaoglu and J. H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," ICCAD, pp. 283-288, Nov. 1998.
3. V. Iyengar, K. Chakrabarty, and B. T. Murray, "Built-in Self Testing of Sequential Circuits Using Precomputed Test Sets," 16th VLSI Test Symposium, pp. 418-423, 1998.
4. A. Jas, J. Ghosh-Dastidar, and N. A. Tuba, "Scan Vector Compression/Decompression Using Statistical Coding," VLSI Test Symposium, pp. 114-120, April 1999.
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7. H. Ichihara, K. Kinoshita, I. Pomeranz, S. M. Reddy, "Test Transformation to Improve Compaction by Statistical Encoding," International Conf. on VLSI Design, pp.294-299, Jan. 2000.
8. S. Kajihara, K. Miyase, "On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits," ICCAD-2001, Nov. 2001.