Low power BIST via non-linear hybrid cellular automata

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 29-34

  Corno, Fulvio ^a   Rebaudengo, Maurizio ^a   Reorda, Matteo Sonza ^a   Squillero, Giovanni ^a   Violante, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; RELIABILITY; VLSI CIRCUITS;

CELLULAR AUTOMATA; FAULT COVERAGE; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 0033751555     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)

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