Static compaction techniques to control scan vector power dissipation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 35-40

  Sankaralingam, Ranganathan ^a   Oruganti, Rama Rao ^a   Touba, Nur A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FLIP FLOP CIRCUITS;

CIRCUIT UNDER TEST; POWER DISSIPATION; SCATIC COMPACTION;

BUILT-IN SELF TEST;

EID: 0033751823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (13)