A modified clock scheme for a low power BIST test pattern generator

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 306-311

  Girard, P ^a   Guiller, L ^a   Landrault, C ^a   Pravossoudovitch, S ^a   Wunderlich, H J ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; SWITCHING CIRCUITS;

CELLULAR AUTOMATA; CLOCK TREE FEEDING; GATED CLOCK SCHEME; LOW POWER TESTING; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 0035018934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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