Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Electronics Letters

Volumn 37, Issue 24, 2001, Pages 1434-1436

  Rosinger, P ^a   Gonciari, P T ^a   Al Hashimi, B M ^a   Nicolici, N ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

SCAN POWER DISSIPATION; SCAN POWER MINIMISATION; SYSTEMS ON CHIP TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0035935883     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010981     Document Type: Article

References (4)

1. A distributed BIST control scheme for complex VLSI devices
2. Minimisation of power dissipation during test application in full scan sequential circuits using primary input freezing
3. Combining low-power scan testing and test data compression for system-on-a-chip
4. Techniques for minimizing power dissipation in scan and combinational circuits during test application