Test set compaction algorithms for combinational circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 283-289

  Hamzaoglu, Ilker ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; HEURISTIC METHODS; MATHEMATICAL MODELS; VECTORS;

ESSENTIAL FAULT REDUCTION (EFR); REDUNDANT VECTOR ELIMINATION (RVE); TEST SET COMPACTION ALGORITHMS;

INTEGRATED CIRCUIT TESTING;

EID: 0032320384     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.288615     Document Type: Conference Paper

References (14)