Test vector compression using EDA-ATE synergies

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 97-102

  Khoche, A ^a   Volkerink, E ^a   Rivoir, J ^a   Mitra, S ^b  

^a AGILENT TECHNOLOGIES   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Automatic test equipment; Automatic test pattern generation; Automatic testing; Bandwidth; Built in self test; Electronic design automation and methodology; Electronic equipment testing; Process design; Test data compression; Vectors

Indexed keywords

AUTOMATIC TESTING; BANDWIDTH; BANDWIDTH COMPRESSION; BUILT-IN SELF TEST; COMPUTER AIDED DESIGN; DATA COMPRESSION; DESIGN; DESIGN FOR TESTABILITY; ELECTRONIC DESIGN AUTOMATION; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT TESTING; EQUIPMENT; EQUIPMENT TESTING; INTEGRATED CIRCUIT TESTING; OSCILLATORS (ELECTRONIC); PROCESS DESIGN; VECTORS;

AUTOMATIC TEST EQUIPMENT; AUTOMATIC TEST PATTERN GENERATION TOOLS; COMPRESSION TECHNIQUES; ELECTRONIC DESIGN AUTOMATION AND METHODOLOGIES; FINE GRAINED; INDUSTRIAL NETWORKS; TEST DATA COMPRESSION; TEST VECTORS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84948405377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011118     Document Type: Conference Paper

References (23)

1. International Technology Roadmap for Semiconductors (ITRS), 1999.
2. G. Hetheringten, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan and J. Rajski, "LBIST for Large Industrial Designs", Proc. Of Inter-national Test Conference", pp. 358-367, 1999.
3. A. Chandra and K. Chakravarty, "Test Data Compression and Decompression for System-on-a-chip using Golomb codes", VLSI Test Symposium, pp. 113-120,2000.
4. A. Khoche, J. Rivoir, "I/O Bandwidth Bottleneck for Test:Is it Real?" IEEE Test Resource Partitioning Workshop, pp. 2.3-1-2.3-6, 2000.
5. M. Ishida, D.S Ha and T. Yamaguchi, "COMPACT: A Hybrid Method for Compressing Test Data", VLSI Test Symposium, pp. 62-69, 1998.
6. A. Chandra and K. Chakravarty, "Frequency Directed Run-length Codes with applications to System-on-a-chip", VLSI Test Symposium, 2001.
7. B. Koenemann, "LFSR-Coded Test Patterns for scan Designs", Proceedings of European Test Conference", pp237-242, 1991.
8. S. Hellerbrand, J. Rajski, S Tarnick, S. Venkatraman and B. Courtois, "Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers", IEEE Transaction on Computers, vol 44, No. 2, pp223-233, Feb, 1995.
9. A. Jas, J. Ghosh Dastidar and N. A. Touba, "Scan Vector Compression Using Statistical Coding", VLSI Test Symposium, pp. 114-120, 1999.
10. I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", Design Automation Conference, pp. 151-155, 2001.
11. P. H. Bardell, W. H. McAnney and J. Savir, "Built-in Test For VLSI: Pseudo-random Techniques", Wiley Inter-Science, 1987.
12. B. Koenemann, "SMARTBIST", Presentation by IBM at ITC 2000.
13. G. Kiefer and H-J. Wunderlich, "Application of Deterministic Logic BIST on Industrial Circuits", International Test Conference (ITC). pp. 105-114, 2000
14. K. Barnhart, B. Keller, B. Konenmann, R. Walther, "OPMISR: Accelerated scan with On product signatures", ITC 2001.
15. M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing, for digital, memory and mixed signal VLSI circuits", Kluwer Academic Publishers, 2000.
16. N.A. Touba and E.J. McCluskey, "Altering a Pseudo-Random Sequence of Bits for Scan-Based BIST", Proc. of IEEE International Test Conference (ITC), pp. 167-175, 1996.
17. C.V. Krishna, A. Jas, and N.A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of IEEE International Test Conference (ITC), pp. 885-893, 2001.
18. S. Mitra, K. S. Kim, "X-compact: An Efficient Response Compaction for Test Cost Reduction", Submitted to ITC 2002.
19. B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, D. Wheater, "A SmartBIST Variant with Guaranteed Encoding", IEEE Test Resource Partitioning Workshop, pp.2.4.1-6, 2001
20. Tetramax User's manual, Synopsys Inc.
21. F. F. Hsu, K. M. Butler, J. H. Patel, "A Case Study on the Implementation of the Illinois Scan Architecture," 2001 IEEE Int. Test Conf., pp. 538-547, Oct.-Nov. 2001.
22. E. J. McCluskey., and C.W. Tseng, "Stuck-Fault Tests vs. Actual Defects," Proc. 2000 International Test Conference, Atlantic City, 2000.
23. TestKompress datasheet, http://www.mentor.com/dft/testkompress/test-kompress-ds.pdf