SCOPUS 정보 검색 플랫폼

IEEE Design and Test of Computers

Volumn 18, Issue 5, 2001, Pages 80-91

Test resource partitioning for SOCs

(2) Chandra, Anshuman a,b Chakrabarty, Krishnendu a

a DUKE UNIVERSITY (United States)

b Duke University (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEM ON A CHIP (SOC); TEST RESOURCE PARTITIONING (TRP);

CHANNEL CAPACITY; CHIP SCALE PACKAGES; COSTS; DATA COMPRESSION; DATA REDUCTION; DATA STORAGE EQUIPMENT; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; QUALITY CONTROL; SIGNAL ENCODING;

INTEGRATED CIRCUIT TESTING;

EID: 0035445025 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/54.953275 Document Type: Article

Times cited : (31)

References (10)

1
- 0029544860
- Acceleration techniques for dynamic vector compaction
- IEEE CS Press, Los Alamitos, Calif.
- (1995) Proc. Int'l Conf. Computer-Aided Design , pp. 310-317
- Raghunathan, A.¹ Chakradhar, S.T.²

2
- 0032306487
- Static compaction using overlapped restoration and segment pruning
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. Int'l Conf. Computer-Aided Design , pp. 140-146
- Bommu, S.¹ Chakradhar, S.T.² Doreswamy, K.B.³

3
- 0032313243
- Stuck-at tuple-detection: A fault model based on stuck-at faults for improved defect coverage
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. IEEE VLSI Test Symp. , pp. 289-294
- Pomeranz, I.¹ Reddy, S.M.²

4
- 0033322164
- Deterministic built-in pattern generation for sequential circuits
- Aug.-Oct.
- (1999) J. Electronic Testing: Theory and Applications (JETTA) , vol.15 , pp. 97-115
- Iyengar, V.¹ Chakrabarty, K.² Murray, B.T.³

5
- 0032318126
- Test vector decompression via cyclical scan chains and its application to testing core-based design
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. Int'l Test Conf. , pp. 458-464
- Jas, A.¹ Touba, N.A.²

6
- 0035271735
- System-on-a-chip test data compression and decompression architectures based on golomb codes
- Mar.
- (2001) IEEE Trans. Computer-Aided Design , vol.20 , Issue.3 , pp. 355-368
- Chandra, A.¹ Chakrabarty, K.²

7
- 0034994812
- Frequency-Directed Run-Length (FDR) codes with application to system-on-a-chip test data compression
- IEEE CS Press, Los Alamitos, Calif.
- (2001) Proc. IEEE VLSI Test Symp. , pp. 42-47
- Chandra, A.¹ Chakrabarty, K.²

8
- 0032309767
- High-speed serializing/de-serializing design-for-test methods for evaluating a 1 GHz microprocessor
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. IEEE VLSI Test Symp. , pp. 234-238
- Heidel, D.¹

9
- 0032320384
- Test set compaction algorithms for combinational circuits
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. Int'l Conf. Computer-Aided Design , pp. 283-289
- Hamzaoglu, I.¹ Patel, J.H.²

10
- 84893648051
- Efficient test data compression and decompression for system-on-a-chip using internal scan chains and golomb coding
- IEEE CS Press, Los Alamitos, Calif.
- (2001) Proc. Design, Automation and Test in Europe (DATE 01) Conf. , pp. 145-149
- Chandra, A.¹ Chakrabarty, K.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.