Scan Array solution for testing power and testing time

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 652-659

  Xu, Lei ^a   Sun, Yihe ^a   Chen, Hongyi ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COMBINATORIAL MATHEMATICS; DESIGN FOR TESTABILITY; OPTIMIZATION;

POWER ESTIMATION ALGORITHMS;

INTEGRATED CIRCUIT TESTING;

EID: 0035687339     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Two techniques for minimizing power dissipation in scan circuits during test application
2. ATPG for heat dissipation minimization during test application
3. Optimal vector selection for low power BIST
4. Design and synthesis of low power weighted random pattern generator considering peak power reduction
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6. Low power BIST design by hypergraph partitioning: Methodology and architectures
7. Minimized power consumption for scan-based BIST
8. BIST and delay fault detection
9. Accumulator-based BIST approach for stuck-open and delay fault testing
10. Built-in test for CMOS circuits