Static test compaction for synchronous sequential circuits based on vector restoration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 7, 1999, Pages 1040-1049

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a IA United States   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; DECISION THEORY; INTEGRATED CIRCUIT TESTING; VECTORS;

FAULT COVERAGE; PARALLEL FAULT SIMULATOR; STATIC TEST COMPACTION; SYNCHRONOUS SEQUENTIAL CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0032691955     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.771184     Document Type: Article

References (10)

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2. R. K. Roy T. M. Niermann J. H. Patel J. A. Abraham and R. A. Saleh Compaction of ATPG-generated test sequences for sequential circuits in Proc. Int. Conf. Computer-Aided Design Nov. 1988 pp. 382-385.
3. B. So Time-efficient automatic test pattern generation systems Ph.D. thesis Dept. Electr. Eng. Univ. Wisconsin at Madison Madison 1994.
4. M. S. Hsiao E. M. Rudnick and J. H. Patel Fast algorithms for static compaction of sequential circuit test vectors in Proc. VLSI Test Symp. Apr. 1997 pp. 188-195.
5. M. S. Hsiao and S. T. Chakradhar State relaxation based subsequence removal for fast static compaction in sequential circuits in Proc. Conf. Design Automation and Test Feb. 1998 pp. 577-582.
6. F. Corno P. Prinetto M. Rebaudengo and M. S. Reorda New static compaction techniques of test sequences for sequential circuits in Proc. 1997 European Design and Test Conf. Mar. 1997 pp. 37-43.
7. H. K. Lee and D. S. Ha HOPE: An efficient parallel fault simulator for synchronous sequential circuits in Proc. 1992 Design Automation Conf. June 1992 pp. 336-340.
8. _ New techniques for improving parallel fault simulation in synchronous sequential circuits in Proc. 1993 Int. Conf. Computer-Aided Design Oct. 1993 pp. 10-17.
9. T. Niermann and J. H. Patel HITEC: A test generation package for sequential circuits in Proc. European Design Automation Conf. 1991 pp. 214-218.
10. M. S. Hsiao E. M. Rudnick and J. H. Patel Sequential circuit test generation using dynamic state traversal in 1996 European Design and Test Conf. Mar. 1996 pp. 22-28.