Power profile manipulation: A new approach for reducing test application time under power constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 10, 2002, Pages 1217-1225

  Rosinger, Paul M ^a   Al Hashimi, Bashir M ^a   Nicolici, Nicola ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

Digital system testing; Nondestructive testing; Power constrained test scheduling

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; HAMILTONIANS; ITERATIVE METHODS; MATHEMATICAL MODELS; SCHEDULING;

DIGITAL SYSTEM TESTING; GLOBAL PEAK POWER APPROXIMATION MODEL; POWER CONSTRAINED TEST SCHEDULING; POWER PROFILE MANIPULATION;

INTEGRATED CIRCUIT TESTING;

EID: 0036810725     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.802256     Document Type: Article

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