Test volume and application time reduction through scan chain concealment

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 151-155

  Bayraktaroglu, I ^a   Orailoglu, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; DATA COMPRESSION; DECODING;

SCAN CHAIN INPUTS (SCI);

CHIP SCALE PACKAGES;

EID: 0034848095     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378388     Document Type: Conference Paper

References (17)

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11. HOPE: An efficient parallel fault simulator
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14. PASTA: Partial scan to enhance test compaction
15. On linear dependencies in subspaces of LFSR-generated sequences
16. Static compaction techniques to control scan vector power dissipation