A case study on the implementation of the Illinois Scan Architecture

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 538-547

  Hsu, Frank F ^a   Butler, Kenneth M ^a   Patel, Janak H ^a  

^a Dallas Semiconductor   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DATA STORAGE EQUIPMENT; LOGIC GATES; VLSI CIRCUITS;

AUTOMATIC TEST EQUIPMENTS (ATE); FUNCTIONAL PATTERN TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0035687712     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966672     Document Type: Article

References (15)

1. An algorithm to reduce test application time in full scan designs
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3. Testing the monster chip
4. A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data
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6. Logic BIST for large industrial designs: Real issues and case studies
7. Applications of deterministic logic BIST on industrial circuits
8. Reducing test data volume using external/LBIST hybrid test patterns
9. Robust delay-fault test generation and synthesis for testability under standard scan design methodology
10. Test vector decompression via cyclical scan chains and its application to core-based designs
11. Frequency-directed run length (FDR) codes with application to system-on-chip test data compression
12. Reducing test application time for full scan embedded cores
13. Self-testing of multichip logic modules
14. Using a single input to support multiple scan chains
15. Transition fault simulation