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Volumn , Issue , 2002, Pages 604-611

Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; EXPERIMENTAL COMPARISON; PRE-PROCESSING STEP; SYSTEM-ON-A-CHIP TEST; SYSTEMS-ON-A-CHIP; TEST APPLICATION TIME; TEST DATA COMPRESSION; THREE PARAMETERS;

EID: 84893771642     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998363     Document Type: Conference Paper
Times cited : (124)

References (16)
  • 2
    • 0034994812 scopus 로고    scopus 로고
    • Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression
    • Apr.
    • A. Chandra and K. Chakrabarty. Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. In Proceedings IEEE VLSI Test Symposium, 114-121, Apr. 2001.
    • (2001) Proceedings IEEE VLSI Test Symposium , pp. 114-121
    • Chandra, A.1    Chakrabarty, K.2
  • 3
    • 0035271735 scopus 로고    scopus 로고
    • System-on-a-chip test data compression and decompression architectures based on Golomb codes
    • Mar.
    • A. Chandra and K. Chakrabarty. System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes. IEEE Transactions on Computer-Aided Design, 20:113-120, Mar. 2001.
    • (2001) IEEE Transactions on Computer-Aided Design , vol.20 , pp. 113-120
    • Chandra, A.1    Chakrabarty, K.2
  • 5
    • 0035015857 scopus 로고    scopus 로고
    • A geometric-primitives- based compression scheme for testing systems-on-chip
    • Apr.
    • A. El-Maleh, S. al Zahir, and E. Khan. A Geometric-Primitives- Based Compression Scheme for Testing Systems-on-Chip. In Proceedings IEEE VLSI Test Symposium, 114-121, Apr. 2001.
    • (2001) Proceedings IEEE VLSI Test Symposium , pp. 114-121
    • El-Maleh, A.1    Al Zahir, S.2    Khan, E.3
  • 11
    • 0032318126 scopus 로고    scopus 로고
    • Test vector decompression via cyclical scan chains and its application to testing core-based designs
    • Oct.
    • A. Jas and N. Touba. Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs. In Proceedings IEEE International Test Conference, 458-464, Oct. 1998.
    • (1998) Proceedings IEEE International Test Conference , pp. 458-464
    • Jas, A.1    Touba, N.2
  • 12
    • 0033297638 scopus 로고    scopus 로고
    • Using an embedded processor for efficient deterministic testing of systems-on-a-chip
    • Oct.
    • A. Jas and N. Touba. Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. In Proceedings International Conference on Computer Design, 418-423, Oct. 1999.
    • (1999) Proceedings International Conference on Computer Design , pp. 418-423
    • Jas, A.1    Touba, N.2
  • 15
    • 0027629018 scopus 로고
    • Compactest: A method to generate compact test set for combinational circuits
    • July
    • I. Pomeranz, L. Reddy, and S. Reddy. Compactest: A method to generate compact test set for combinational circuits. IEEE Transactions on Computer-Aided Design, 12:1040-1049, July 1993.
    • (1993) IEEE Transactions on Computer-Aided Design , vol.12 , pp. 1040-1049
    • Pomeranz, I.1    Reddy, L.2    Reddy, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.