-
2
-
-
0034994812
-
Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression
-
Apr.
-
A. Chandra and K. Chakrabarty. Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. In Proceedings IEEE VLSI Test Symposium, 114-121, Apr. 2001.
-
(2001)
Proceedings IEEE VLSI Test Symposium
, pp. 114-121
-
-
Chandra, A.1
Chakrabarty, K.2
-
3
-
-
0035271735
-
System-on-a-chip test data compression and decompression architectures based on Golomb codes
-
Mar.
-
A. Chandra and K. Chakrabarty. System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes. IEEE Transactions on Computer-Aided Design, 20:113-120, Mar. 2001.
-
(2001)
IEEE Transactions on Computer-Aided Design
, vol.20
, pp. 113-120
-
-
Chandra, A.1
Chakrabarty, K.2
-
5
-
-
0035015857
-
A geometric-primitives- based compression scheme for testing systems-on-chip
-
Apr.
-
A. El-Maleh, S. al Zahir, and E. Khan. A Geometric-Primitives- Based Compression Scheme for Testing Systems-on-Chip. In Proceedings IEEE VLSI Test Symposium, 114-121, Apr. 2001.
-
(2001)
Proceedings IEEE VLSI Test Symposium
, pp. 114-121
-
-
El-Maleh, A.1
Al Zahir, S.2
Khan, E.3
-
7
-
-
0032309767
-
High-speed serialiazing/deserializing design-for-test methods for evaluating a 1 ghz microprocessor
-
Apr.
-
D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, and K. Stawiasz. High-speed serialiazing/deserializing design-for-test methods for evaluating a 1 ghz microprocessor. In Proceedings IEEE VLSI Test Symposium, 234-238, Apr. 1998.
-
(1998)
Proceedings IEEE VLSI Test Symposium
, pp. 234-238
-
-
Heidel, D.1
Dhong, S.2
Hofstee, P.3
Immediato, M.4
Nowka, K.5
Silberman, J.6
Stawiasz, K.7
-
11
-
-
0032318126
-
Test vector decompression via cyclical scan chains and its application to testing core-based designs
-
Oct.
-
A. Jas and N. Touba. Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs. In Proceedings IEEE International Test Conference, 458-464, Oct. 1998.
-
(1998)
Proceedings IEEE International Test Conference
, pp. 458-464
-
-
Jas, A.1
Touba, N.2
-
12
-
-
0033297638
-
Using an embedded processor for efficient deterministic testing of systems-on-a-chip
-
Oct.
-
A. Jas and N. Touba. Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. In Proceedings International Conference on Computer Design, 418-423, Oct. 1999.
-
(1999)
Proceedings International Conference on Computer Design
, pp. 418-423
-
-
Jas, A.1
Touba, N.2
-
13
-
-
0035704290
-
A SmartBIST variat with guaranteed encoding
-
Nov.
-
B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater. A SmartBIST Variat with Guaranteed Encoding. In Proceedings of the Asian Test Symposium, 325-330, Nov. 2001.
-
(2001)
Proceedings of the Asian Test Symposium
, pp. 325-330
-
-
Koenemann, B.1
Barnhart, C.2
Keller, B.3
Snethen, T.4
Farnsworth, O.5
Wheater, D.6
-
14
-
-
0033316969
-
Towards a standard for embedded core test: An example
-
Sept.
-
E. J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel. Towards a Standard for Embedded Core Test: An Example. In Proceedings IEEE International Test Conference, 616-627, Sept. 1999.
-
(1999)
Proceedings IEEE International Test Conference
, pp. 616-627
-
-
Marinissen, E.J.1
Zorian, Y.2
Kapur, R.3
Taylor, T.4
Whetsel, L.5
-
15
-
-
0027629018
-
Compactest: A method to generate compact test set for combinational circuits
-
July
-
I. Pomeranz, L. Reddy, and S. Reddy. Compactest: A method to generate compact test set for combinational circuits. IEEE Transactions on Computer-Aided Design, 12:1040-1049, July 1993.
-
(1993)
IEEE Transactions on Computer-Aided Design
, vol.12
, pp. 1040-1049
-
-
Pomeranz, I.1
Reddy, L.2
Reddy, S.3
|